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HD151011
Dual BCD Programmable Counter with Synchronous Preset Enable
REJ03D0298-0200Z (Previous ADE-205-100 (Z)) Rev.2.00 Jul.16.2004
Description
The HD151011 has BCD decimal two digits down counter and D-type Flip Flop. The counter can set up to max 99 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider.
Features
* High speed operation tpd (CLK or CLK to Q) = 35 ns (typ) * High output current Fanout of 10 LS TTL Loads * Wide operating voltage VCC = 2 to 6 V * Low supply current (Ta = 25C) ICC (Static) = 4 A (max) * Ordering Information
Part Name HD151011FPEL HD151011TELL Package Type Package Code FP T Package Abbreviation Taping Abbreviation (Quantity) EL (2,000 pcs/reel) ELL (2,000 pcs/reel)
SOP-20 pin (JEITA) FP-20DAV TSSOP-20 pin TTP-20DAV
Note: Please consults the sales office for the above package availability.
Rev.2.00, Jul.16.2004, page 1 of 13
HD151011
Function Table
Control Inputs CLR H X -- -- L H Note: H X -- -- H L 1. 2. 3. 4. PR H L -- -- -- -- SPE X X H L -- -- C/T T Mode Generally count Synchronous preset -- -- Initialize of Q output Initialize of Q output Operation Description Down count at the rise edge of clock (CLK) Down count at the fall edge of clock (CLK) Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) Clock inputs (CLK, CLK) is CMOS level Clock inputs (CLK, CLK) is TTL level Initialize of Q = "L" Initialize of Q = "H"
H L X --
: : : :
Synchronous preset (SPE) input can set max 99 down counts. When the count value is 0, the next clock pulse presets the data to invert the output. CLR and PR inputs initialize output state. Clock inputs (CLK, CLK) is selectable CMOS level (VCC = 2.0 to 6.0 V) and TTL level (VCC = 4.5 to 5.5V) (Jn, C/T, PR, CLR and SPE inputs are CMOS level) Don't set data exceeding 99 to Jn. (J0 : LSB, J7 : MSB) High level Low level Immaterial Irrespective of condition
Pin Arrangement
CO 1 J0 2 J1 3 J2 4 J3 5 J4 6 J5 7 J6 8 J7 9 GND 10
20 VCC 19 (Test 1) * 18 (Test 2) * 17 C / T 16 CLK 15 CLK 14 Q 13 PR 12 SPE 11 CLR
(Top view)
Rev.2.00, Jul.16.2004, page 2 of 13
HD151011
Pin Description
Pin Name Input pins J0 to J7 C/T CLK, CLK SPE PR CLR Output pins CO Q Pin Description Count data input for option Level change input for CLK, CLK (CMOS level or TTL level) Clock inputs Preset input for Jn data Preset input for D-type Flip Flop (Initialize "L" at Q output) Clear input for D-type Flip Flop (Initialize "H" at Q output) Output for BCD decimal counter Output for D-type Flip Flop CLK : Rise edge trigger CLK : Fall edge trigger
Absolute Maximum Ratings
Item Supply voltage Input/output voltage VCC, GND current Output current/pin Power dissipation Storage temperature Symbol VCC VIN/VOUT ICC, IGND IOUT PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 50 25 757 -65 to 150 V V mA mA mW C Unit
Input diode current IIK 20 mA Output diode current IOK 20 mA Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Input/output voltage Operating temperature Input rise/fall time*1 VCC = 2.5 V VCC = 4.5 V VCC = 5.5 V Note: Symbol VCC VIN/OUT Topr tr, tf 2 0 -40 0 0 0 Min -- -- -- -- -- -- Typ 6 VCC +85 1000 500 400 Max V V C ns Unit
1. This item guarantees maximum limit when one input switches.
Logic Diagram
C/T J0 J1 J2 J3 J4 J5 J6 J7 J0
BCD decimal counter
CLK CLK CLK CO PR PR D CO SPE CK CLR SPE CLR Q Q Q
J1 J2 J3 J4 J5 J6 J7
Rev.2.00, Jul.16.2004, page 3 of 13
HD151011
Electrical Characteristics
SymItem High level input voltage bol VIH VCC 2.0 4.5 6.0 2.0 4.5 Ta = 25C Ta = -40 to 85C Test Conditions
Min Typ Max Min Max Unit 1.5 -- -- 1.5 -- V J0 to J7 3.15 4.2 1.5 3.15 -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 4.5 6.0 4.31 5.80 0.0 0.0 0.0 0.17 0.18 -- -- -- -- -- -- -- -- 0.5 1.35 1.8 0.5 1.35 1.8 0.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 3.15 4.2 1.5 3.15 4.2 2.0 -- -- -- -- -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 0.5 1.35 1.8 0.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40.0 A A V VIN = VIH or VIL V VIN = VIH or VIL V J0 to J7 C/T, SPE PR, CLR CLK, CLK C/T, SPE PR, CLR CLK, CLK
C/T = VIH
6.0 4.2 4.5 to 2.0 5.5 Low level input voltage VIL 2.0 4.5 6.0 2.0 4.5 6.0 -- -- -- -- -- --
C/T = VIL
C/T = VIH
High level output voltage
VOH
4.5 to -- 5.5 2.0 1.9 4.5 6.0 4.5 6.0 4.4 5.9 4.18 5.68 -- -- -- -- -- -- --
C/T = VIL IOH = -20 mA
IOH = -4 mA IOH = -5.2 mA IOL = 20 mA
Low level output voltage
VOL
2.0 4.5 6.0 4.5
IOL = 4 mA IOL = 5.2 mA VIN = VCC or GND VIN = VCC or GND
Input capacitance Supply current
IIN ICC
6.0 6.0 6.0
Rev.2.00, Jul.16.2004, page 4 of 13
HD151011
Switching Characteristics (CL = 50 pF, tr = tf = 6 ns)
SymItem Maximum clock frequency Output rise/fall time tTLH tTHL bol fmax Ta = 25C Ta = -40 to 85C Test Conditions
VCC Min Typ Max Min Max Unit 2.0 -- -- 4 -- 3 MHz 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 100 20 17 15 10 5 -- 36 -- 30 8 7 -- 30 -- -- 35 -- -- 18 -- -- -- -- -- -- -- -- -- -- 5 20 24 75 15 13 250 50 45 300 60 53 150 30 25 -- -- -- -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 125 25 21 15 10 5 -- 16 19 95 19 16 318 63 53 380 75 65 185 38 32 -- -- -- -- -- -- -- -- -- 10 ns ns ns
Propagation delay time tPLH tPHL tPLH tPHL tPLH tPHL Pulse width (CLK, CLK, PR, CLR) Setup time (Jn - CLK, CLK) (SPE, CLK, CLK) Hold time (Jn - CLK, CLK) (SPE, CLK, CLK) Input capacitance th tw
ns
CLK or CLK to CO
CLK or CLK to Q
PR or CLK to Q
ts
ns
2.0 4.5 6.0 --
CIN
pF
Power dissipation CPD -- -- 48 -- -- -- pF capacitance*1 Note: 1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. ICC (opr) = CPD * VCC * fIN + ICC
Rev.2.00, Jul.16.2004, page 5 of 13
HD151011 Test Circuit
VCC Input Pulse generator
See Function Table
VCC
J0 J1 Output Q Output J7 C/T CLK CLK SPE PR CLR CL CL CO
Zout = 50 Input Pulse generator Zout = 50
Note:
1. CL includes probe and jig capacitance.
Waveforms - 1
tw 6 ns tw 6 ns 90 % 90 % *1 *1 V ref V ref 10 % t PLH 90 % 10 % t PHL 90 % 50 % 10 % t THL t PHL 90 % 90 % 50 % 10 % t THL *1
CLK
VIH
CLK
GND
VOH
Q
10 %
50 % t TLH t PLH
VOL
VOH
CO
10 %
50 % t TLH
VOL
Note:
1. In case of C/T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC, Vref is VCC x 50%
Rev.2.00, Jul.16.2004, page 6 of 13
HD151011 Waveforms - 2
6 ns 90 % 90 % 50 % 10 % 10 % ts
VCC
Jn
GND
90 % *1 V ref
CLK
VIH
*1
CLK
10 %
10 % 6 ns
GND VOH
50 %
F/F Output
*2
Internal delay
VOL
Waveforms - 3
6 ns 90 % 90 % 50 % 10 % th 10 %
VCC
Jn
GND VIH
*1
CLK
*1 V ref
90 %
CLK
10 %
10 % 6 ns
GND VOH
50 %
*2
F/F Output
Internal delay
VOL
Notes:
1. In case of C/T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC, Vref is VCC x 50% 2. F/F output is internal signal of IC.
Rev.2.00, Jul.16.2004, page 7 of 13
HD151011 Waveforms - 4
6 ns 90 % 90 % 50 % 10 % 10 % ts
VCC
SPE
GND
90 % *1 V ref
CLK
VIH
*1
CLK
10 %
10 % 6 ns
GND VOH
50 %
F/F Output
*2
Internal delay
VOL
Waveforms - 5
6 ns 90 % 90 % 50 % 10 % th 10 %
VCC
SPE
GND VIH
*1
CLK
*1 V ref
90 %
CLK
10 %
10 % 6 ns
GND VOH
50 %
*2
F/F Output
Internal delay
VOL
Notes:
1. In case of C/T = "L", CLK, CLK is VIH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is VIH = VCC, Vref is VCC x 50% 2. F/F output is internal signal of IC.
Rev.2.00, Jul.16.2004, page 8 of 13
HD151011 Waveforms - 6
tf 90 % tr 90 % 50 % 10 % tw tf 90 % tr 90 % 50 % 10 % tw t PHL t PLH
VCC
CLR
50 % 10 %
GND
VCC
PR
50 % 10 %
GND
VOH Q
50 % 50 %
VOL
Rev.2.00, Jul.16.2004, page 9 of 13
HD151011
Timing Chart
CLK
SPE
J0
J1
J2
J3
J4
J5
J6
J7
(CO=SPE)
CLR (Initialize of CLR) Q
PR (Initialize of PR) Q
Count
5
4
3
2
1
0
3
2
1
0
23
22
Rev.2.00, Jul.16.2004, page 10 of 13
HD151011
Example of Application Circuit
AC Signal Generator for STN Type Liquid Crystal Panel CLK (CLK) : Initialize counter CMOS level input : 32
CO J0 J1 J2 J3 J4 J5 J6 J7 GND V CC (Test 1) (Test 2) C/T CLK CLK Q PR SPE CLR * * NC NC
Note:
When initializing output D-F/F apply "L"
Rev.2.00, Jul.16.2004, page 11 of 13
HD151011
Timing Chart
Example of AC Signal Generator
1 2 3 31 32 33 34 35 65 66 67 68
CLK
SPE J0
J1 1digit=2 J2
J3
J4
J5 2digits=3 J6
J7
(CO=SPE)
CLR
Q
PR
Q
Count
32
31
30
2
1
0
32
31
1
0
32
31
Rev.2.00, Jul.16.2004, page 12 of 13
HD151011
Package Dimensions
As of January, 2003
12.6 13 Max
20
Unit: mm
11
1
10
5.5
0.80 Max
2.20 Max
*0.20 0.05
0.20 7.80 + 0.30 -
1.15
1.27
*0.40 0.06
0.10 0.10
0 - 8
0.70 0.20
0.15
0.12 M
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
FP-20DAV -- Conforms 0.31 g
As of January, 2003
Unit: mm
6.50 6.80 Max 20 11
4.40
1
10 0.65 1.0 6.40 0.20 0.65 Max
*0.15 0.05
*0.20 0.05
0.13 M
1.10 Max
0.10
0.07 +0.03 -0.04
0 - 8
0.50 0.10
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-20DAV -- -- 0.07 g
Rev.2.00, Jul.16.2004, page 13 of 13
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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